Mixed equation-simulation circuit optimization
Abstract/Contents
- Abstract
- One of the main challenges in designing analog circuits today is to cope with the complex behaviors of modern devices. For example, the drain current of a deep- submicron MOSFET device can no longer be predicted by the long-channel models, due to various effects including carrier velocity saturation, vertical-field induced mobility degradation, drain-induced barrier lowering (DIBL), and narrow channel effects, to name only a few. In addition, the characteristics of each individual device can be further affected by random variability and proximity effects. As a result, it is extremely difficult to design an optimal circuit at the presence of these complex phenomena without relying on computational aids, e.g. circuit optimizers. However, many circuit optimizers based on global optimization techniques such as simulated annealing or evolutionary algorithms may also have difficulties unless they are provided with good initial guesses. This research focuses on building a circuit optimizer that leverages designer's intent to help the simulation-based optimizers find solutions quickly. The technique is inspired by continuation techniques in numerical analysis where a difficult problem is solved by constructing an easier problem first and gradually refining its solution to that of the hard problem. In a circuit optimization context, the designer's simplified equations for the circuit serve as the easier problem. These simplified design equations are easy to write as they need not be completely accurate and have solutions that are easy to reason about. While these design equations may not generate a good initial design for optimizing real circuits directly, they can help guide the optimizer towards an optimal solution by constructing and solving a series of intermediate problems that gradually change from the initial problem based on design equations to the real circuit problem with accurate device models. Assuming that the solutions to these intermediate problems change only gradually along this path, each problem can be solved very efficiently via local optimization methods, using the solution to the previous problem as a starting point. Although more problems have to be solved, since each is solved very efficiently, the overall computational costs can be lower than that of solving the final problem directly. We apply our circuit optimization approach to several design examples and investigate the importance of the initial designer's equations by comparing our optimizer's performances against those of a local optimizer and a generic continuation- based optimizer. We extend this basic idea to leverage hierarchy to help optimize large circuits, and demonstrate this technique with a PLL design example. Besides the runtime benefit, performing optimization hierarchically is also intuitive and more in line with how a circuit designer would approach designing a large circuit problem like the PLL.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2011 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Jeeradit, Metha |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Boyd, Stephen P |
| Thesis advisor | Murmann, Boris |
| Advisor | Boyd, Stephen P |
| Advisor | Murmann, Boris |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Metha Jeeradit. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph. D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Metha Jeeradit
Also listed in
Loading usage metrics...