High-level digital interfaces with low overhead
Abstract/Contents
- Abstract
- The majority of today's digital designs are coded in hardware description languages (HDLs) such as Verilog, VHDL, BlueSpec, SystemC, etc. HDLs provide useful abstractions to facilitate the design of complex systems, and although they offer diverse syntaxes for expressing hardware, they actually share similar module interface semantics. These interfaces rely on hardwired, timing-dependent communication protocols, and offer poor design-time parameterization of internal control logic, both of which impede complex system design. In this thesis, we describe a high-level interface abstraction that improves upon the hardwired interfaces common to popular HDLs. These high-level interfaces create logically asynchronous connections between modules, allowing module timings to vary without breaking system functionality. This has a number of design advantages, including better design exploration and easier module reuse. Moreover, high-level interfaces abstract hardwired control logic as per-instance module elaboration parameters, further enabling module reuse. These generic, flexible interfaces are rarely used today because they lead to timing and area overheads compared to hardwired, customized designs. To address this, we present a reachability analysis framework that can be used to identify and remove overhead from high-level interfaces in gate-level netlists. This makes the synthesis results of high-level interfaces comparable to typical hardwired approaches. We use various examples from the Stanford Smart Memories project to demonstrate the use of high-level interfaces, and how they can be synthesized into efficient implementations. By building modules with high-level interfaces, system designers can both modify existing designs (e.g., pipeline long paths) and reuse modules to compose new working systems, without worrying about the timing of interface handshakes. Furthermore, reachability analysis ensures high-level interfaces do not add any logic overhead compared to a hardwired interface. Therefore, we believe high-level interfaces are a useful abstraction for extending HDLs as design complexities continue growing into the future.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Kelley, Kyle Ryan |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Kozyrakis, Christoforos, 1974- |
| Thesis advisor | Olukotun, Oyekunle Ayinde |
| Advisor | Kozyrakis, Christoforos, 1974- |
| Advisor | Olukotun, Oyekunle Ayinde |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Kyle R. Kelley. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Kyle Ryan Kelley
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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