High performance III-V PMOSFET
Abstract/Contents
- Abstract
- As scaling of Silicon CMOS technology is only yielding marginal returns, III-V materials are being actively explored as (a) channel materials for future technology nodes for providing high performance at low operating voltages and (b) as enabling materials for optical interconnects. This research is primarily being driven by high electron mobility and direct bandgap in III-V semiconductors. Three major challenges facing the III-V CMOS community right now are (1) development of a III-V pMOSFET with high hole mobility to compliment the III-V nMOSFET (2) development of a high-k dielectric with low interface state densities, suitable for use as gate dielectric (3) integration of III-V materials on Silicon. In this thesis our contributions in overcoming first two challenges and development of an III-V pMOSFET with InGaSb channel material and Al2O3 dielectric will be described. (1) Firstly, we start with bandstructure calculations and modeling to identify the optimal material, strain configuration and heterostructure design for enhancing hole mobility in III-V channels, which had traditionally lagged in comparison to Silicon. (2) Compressively strained InGaSb quantum-well channels, identified from modeling results have been investigated for obtaining high hole-mobility. Parameters such as strain, valence band offset etc. have been experimentally measured. Transport and bandstructure have been quantified by studying these 2D hole gases under high magnetic field. (3) After establishing the feasibility of these materials for hole-transport, we have worked towards development of a pMOSFET with an Sb-based channel. Al2O3 dielectric with mid-bandgap density of interface states of 3 x 1011/cm2eV on GaSb substrate was developed. Finally, surface/buried channel III-V pMOSFETs with sub-threshold slope of 120mV/decade, ION/IOFF > 1 x 104 and having more than 50/100% mobility gain on germanium over the entire sheet range have been fabricated using a sub 350°C self-aligned process flow.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2011 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Nainani, Aneesh |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Nishi, Yoshio, 1940- |
| Primary advisor | Saraswat, Krishna |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Harris, J. S. (James Stewart), 1942- |
| Advisor | Harris, J. S. (James Stewart), 1942- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Aneesh Nainani. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Ph.D. Stanford University 2011 |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Aneesh Nainani
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