Switched-capacitor DACs using open loop output drivers and digital predistortion
- High-speed communication systems, such as the 10 Gb/s Ethernet standard for copper cabling (10GBASE-T), use digital signal processing (DSP) to overcome the noise and bandwidth constraints of communication channels and, thereby, improve network throughput. The sophistication of these DSP techniques is possible because engineers can implement them using very little area and power in modern CMOS processes. And as CMOS technology scales, the power and area costs of digital logic become even more favorable. The requirements of communication systems also put pressure on circuit designers to develop higher-fidelity, higher-speed digital-to-analog converters (DACs). Unfortunately in this case, CMOS technology scaling offers a mixed bag of trends: some favorable to the most prevalent techniques used in DAC design and others unfavorable. The research presented in this dissertation is an attempt to let CMOS scaling trends guide the DAC design process. To this end, we have developed a new DAC architecture that relies on DSP to overcome some of the limitations encountered in analog and mixed signal design. The architecture consists of a digital predistortion block, a switched-capacitor DAC core, an open-loop output driver, a calibration ADC and a calibration algorithm. During normal operation, the predistortion block operates on the input data stream in such a way that nonlinearties in the DAC core and open-loop output driver are cancelled. Because these nonlinearities can change over time, the calibration ADC monitors the DAC output in the background, allowing the calibration algorithm to continuously update the predistortion coefficients. The predistortion block is implemented as a lookup table that re-maps each input sample to a unique internal value. This allows the predistorter to consume low power, but it also limits the kinds of errors that can be cancelled. Only memoryless nonlinearities, which are nonlinearities that are not a function of signal frequency, can be corrected. Existing DAC architectures are not good candidates for this kind of correction because their performance varies significantly across frequency. Therefore, the architecture that we have developed was designed so that its dominant nonlinearity mechanisms are approximately memoryless relative to the frequencies of interest. A 12-bit, 800-MS/s prototype chip demonstrating the new architecture was fabricated in a 90-nm CMOS process. The prototype achieves better than 58 dB SFDR for signal frequencies below 200 MHz and better than 53 dB SFDR for signal frequencies below 400 MHz. The full-scale output current is 16 mA, but by changing the resistive load seen by the DAC, we tested output voltage swings from 0.65 Vppd to 2.9 Vppd. We could discern no difference in SFDR performance for large or small output voltage swings.
|Type of resource
|electronic; electronic resource; remote
|1 online resource.
|Daigle, Clayton Hollis
|Stanford University, Department of Electrical Engineering
|Wooley, Bruce A, 1943-
|Wooley, Bruce A, 1943-
|Statement of responsibility
|Clayton Hollis Daigle.
|Submitted to the Department of Electrical Engineering.
|Ph.D. Stanford University 2010
- © 2010 by Clayton Hollis Daigle
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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