Heterogeneous integration by parallel insertion of chiplets into wafer
Abstract/Contents
- Abstract
- The HIPPI process (Heterogeneous Integration by Palletized Parallel Insertion) embeds CMOS chiplets into MEMS wafers, to bypass the monolithic integration challenges of combining MEMS functionality with CMOS circuitry. Dry alignment is provided by passive guide tabs, which are created through polysilicon refill of front-side etched trenches. The guide tabs are compatible with further processing on the wafer. Precision chiplets are created by through-wafer etching. After chiplet drop-in, optical detection provides feedback of chiplet jamming, and horizontal driving of the chiplets finishes the zero insertion force assembly process. We demonstrate less than 2.5[mu]m of chiplet to substrate alignment error. Theoretical scaling of alignment accuracy reaches numbers comparable to photolithography, allowing high density interconnects for heterogeneous integration without precision manipulators.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Chen, Jeng-Wen |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Howe, Roger Thomas |
| Thesis advisor | Howe, Roger Thomas |
| Thesis advisor | Lee, Thomas |
| Thesis advisor | Solgaard, Olav |
| Advisor | Lee, Thomas |
| Advisor | Solgaard, Olav |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Jeng-Wen Peter Chen. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Jeng-Wen Chen
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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