Array architecture for a nonvolatile 3-dimensional cross-point memory
Abstract/Contents
- Abstract
- This work explores the design and capabilities of a three-dimensional cross-point array structure suitable for use with resistance-change non-volatile memory. The resistance-change cell serves as both the access element and the memory element, eliminating the need for individual selection transistors or diodes. This enables the memory to be fabricated in arrays with a line spacing of F, the minimum feature size for a given process technology. By stacking the cross-point arrays in n layers, we achieve an effective cell size of 4F^2/n. Previous works describing transistor-free memory arrays have been limited by excessive leakage current across unselected bitlines and wordlines during memory access. This work presents novel architecture and circuit techniques that minimize leakage current effects while maintaining a high effective bit density. A test chip fabricated in 0.18 um CMOS technology allows us to verify the architecture and circuit functionality. The performance of a 8 Gb memory chip build in 65 nm technology has been simulated. A random access time of 104 ns is achieved with a power dissipation of 61.2 uW. This makes the 3-D cross-point memory competitive with NOR flash in terms of read time, and competitive with NAND flash in terms of area efficiency.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Ou, Elaine |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Wong, S |
| Thesis advisor | Wong, S |
| Thesis advisor | Lee, Thomas |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Advisor | Lee, Thomas |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Elaine Ou. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Elaine Ou
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