3D vertical resistive switching memory towards ultrahigh-density non-volatile memory

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To meet the exploding information processing and data storage demands, memory technology, as one of the cornerstones in modern computing systems, faces the constant challenge of advancing to the next technology node with a larger capacity and higher density. As difficulties arise in the further scaling of conventional memories, new memories show the potentials to bridge the performance gap between memory and storage, providing new opportunities to innovate computing systems and architectures. Among emerging memories, resistive switching memory (RSM) is a promising solution due to its high device density and reasonably fast write/read operation speed. Resistive random-access memory (RRAM), as an example of RSM, has a simple structure and uses low-temperature fabrication that is compatible with back-end-of-the-line (BEOL) metal wiring of typical CMOS logic technology, thus potentially leading to low cost and on-chip integration with logic for high bandwidth access. Research efforts have been made to explore various material options, device and array structures, and chip architectures. However, to achieve an ultrahigh-density memory, a practical co-design must take into account all the above considerations to arrive at a superior solution. In this dissertation, I present a way to realize ultrahigh-density memory with 3D vertical RRAM (VRRAM). I develop a design guideline for ultrahigh-density 3D VRSM using simulations of 3D memory arrays based on an accurate and computationally efficient model of the memory and parasitic resistance of the memory wired in 3D. I detail the model formulation and validation with physics-based simulations. Combined with simulation results, I discuss design specifications for different physical levels from device to array to chip architecture and provide a comprehensive list of design tasks to achieve an ultrahigh-density 3D VRRAM. To prioritize design tasks among different levels, I focus on the rudimentary design constraints at the device level and extend design requirements to a ready-to-build memory device in the lab. I then experimentally demonstrate an 8-layer 3D Ru/AlOxNy/TiN VRRAM towards an ultrahigh-density memory. This 3D VRRAM satisfies the design requirements for a tera-bit class memory when integrated with a proper selector. I further investigate the downscaling potentials of 3D VRRAM based on experimental data and ongoing scaling techniques and trends in the industry. Incorporating these scaling prospects, I project that 3D VRRAM can achieve a much higher density and capacity with the same number of 3D layers and fewer bits per cell compared to the state-of-the-art 3D NAND. With the structural and process flexibility (e.g., BEOL), 3D VRRAM can expand its high-density applications to be integrated on-chip with CMOS logic for high bandwidth memory access.


Type of resource text
Form electronic resource; remote; computer; online resource
Extent 1 online resource.
Place California
Place [Stanford, California]
Publisher [Stanford University]
Copyright date 2022; ©2022
Publication date 2022; 2022
Issuance monographic
Language English


Author Qin, Shengjun
Degree supervisor Wong, Hon-Sum Philip, 1959-
Thesis advisor Wong, Hon-Sum Philip, 1959-
Thesis advisor Saraswat, Krishna
Thesis advisor Wong, S. Simon
Degree committee member Saraswat, Krishna
Degree committee member Wong, S. Simon
Associated with Stanford University, Department of Electrical Engineering


Genre Theses
Genre Text

Bibliographic information

Statement of responsibility Shengjun Qin.
Note Submitted to the Department of Electrical Engineering.
Thesis Thesis Ph.D. Stanford University 2022.
Location https://purl.stanford.edu/cx989tt3971

Access conditions

© 2022 by Shengjun Qin
This work is licensed under a Creative Commons Attribution 3.0 Unported license (CC BY).

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