Resistive switching random access memory (RRAM) : analysis, modeling, and characterization toward practical applications

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In computing systems, memories are storage devices that keep instructions and data. To balance the performance and cost of modern computing systems, a hierarchy of memories---registers, caches, main memory, and storage---with different speeds and densities (costs) are utilized. In the memory hierarchy, a major performance gap between main memory and storage has become the bottleneck for many data-centric applications. Bridging this performance gap in the hierarchy has been the motivation of the development of many new memories. Among these new memories, resistive switching random access memory (RRAM) is a promising candidate for the next-generation non-volatile memory. Due to its simple structure, direct over-write, bit-alterability, fast speed, and low energy consumption, RRAM shows great potential for being used as both off-chip and on-chip binary digital memories. Additionally, the analog conductance modulation of RRAM allows it to be used as analog weights for machine learning specialized and neuromorphic computing hardware. This thesis presents the analysis, modeling, and characterization of RRAM that enable it to be used in both future digital memory systems and machine learning specialized/neuromorphic computing hardware. In Chapter 1, I review the development of memories in computing systems and the fundamentals of RRAM, followed by a discussion of the challenges for RRAM-based applications. Some of the key challenges include: 1) developing large-scale ultrahigh-density 3D VRRAM memory; 2) modeling of RRAM for circuit- and system-level design explorations; 3) achieving bidirectional analog conductance modulation of RRAM devices for using them as analog weights in the neural networks. These challenges are further discussed and addressed in Chapter 2 to 4 respectively. In Chapter 2, I investigate design guidelines from device to architecture levels to achieve ultrahigh-density 3D vertical resistive switching memory (VRSM). An accurate and computationally efficient simulation platform is developed to establish the write/read margins of 3D VRSM architectures. Using this simulation platform, I analyze the requirements of memory, selector, pillar driving transistors (pillar driver), array layout, and architecture floor plan. The analysis indicates: 1) small footprint pillar drivers are necessary for a high pillar areal density; 2) organizing the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) maximizes array efficiency and chip density; 3) the hexagon array with large low resistance state (LRS) and adequate nonlinearity (NL) is required for ultra-dense 3D VRSM. Compared to the most advanced 3D NAND, 3D VRSM has 46% higher chip density and shows better potential for future ultra-dense storage. In Chapter 3, I develop a dynamic Verilog-A RRAM compact model for circuit- and system-level design explorations. This model not only captures the DC and AC behaviors of RRAM devices, but also includes their intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experimental data is presented and illustrated with a broad set of experimental data using multi-layer and doped RRAM devices. The physical meanings of these model parameters are also discussed. Lastly, I provide an example of applying the RRAM cell model to a TCAM macro. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst-case latency of the memory array. In Chapter 4, I examine the temperature-dependent characterization of RRAM devices using micro thermal stages (MTS) and provide a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. I find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. The results suggest that the filament morphology before SET is the key to understanding this phenomenon: gradual SET is obtained when the filament has a single-layer gap in the RESET state, and abrupt SET is obtained when the filament has a multi-layer gap in the RESET state. Additional temperature-dependent characterization is also applied to the RRAM during forming, read, write, and reliability measurements for both DC and AC conditions. Finally, I conclude the thesis with a summary of contributions and a brief outlook on future work of RRAM. Future work on one selector one RRAM (1S1R) cells and conductance modulation of RRAM devices can further facilitate the development of RRAM-based applications: 1) further investigation is needed to achieve 1S1R cells with large LRS and adequate NL; 2) modeling of bidirectional conductance modulation can be useful for the analysis of RRAM-based neural networks; 3) characterization of the conduction mechanisms and simulations on the conductance modulation during SET can be helpful in understanding the physics behind analog conductance modulation; 4) thermal engineering on the RRAM devices, such as capping layer and thermal insulation, can modulate the analog conductance modulation and improve the characteristics of RRAM for neural networks


Type of resource text
Form electronic resource; remote; computer; online resource
Extent 1 online resource
Place California
Place [Stanford, California]
Publisher [Stanford University]
Copyright date 2020; ©2020
Publication date 2020; 2020
Issuance monographic
Language English


Author Jiang, Zizhen
Degree supervisor Wong, Hon-Sum Philip, 1959-
Thesis advisor Wong, Hon-Sum Philip, 1959-
Thesis advisor Asheghi, Mehdi
Thesis advisor Wong, S. Simon
Degree committee member Asheghi, Mehdi
Degree committee member Wong, S. Simon
Associated with Stanford University, Department of Electrical Engineering.


Genre Theses
Genre Text

Bibliographic information

Statement of responsibility Zizhen Jiang
Note Submitted to the Department of Electrical Engineering
Thesis Thesis Ph.D. Stanford University 2020
Location electronic resource

Access conditions

© 2020 by Zizhen Jiang
This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).

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