Integrating graphene with copper interconnects for future energy-efficient and reliable nanoelectronic systems
Abstract/Contents
- Abstract
- Copper (Cu) interconnects have scaled down concomitantly with transistors for the past two decades. However, further narrowing down of interconnects is constrained by increased resistivity at small dimensions, and by Cu electromigration (EM) reliability problems. Beyond the 16 nm technology node, the global and intermediate interconnect delay is over 1,000 times larger than the transistor delay. For sub-80 nm wire pitch, the problems are exacerbated due to the increasing Cu wire resistivity, (relatively) thick diffusion barrier occupying larger portion of the conduction area, and higher current density stressing the EM reliability. A diffusion barrier layer is required to prevent diffusion of Cu into the surrounding dielectric, causing breakdown or shorting between adjacent Cu wires. To achieve small overall interconnect resistivity, more conductive and thinner barrier materials are needed to replace the industrial-standard TaN barrier, which is non-scalable below 2 nm and has a resistivity of around 260-290 μΩ⋅cm, nearly 150 times larger than that of bulk Cu (~1.67 μΩ∙cm). Meanwhile, a capping layer on top of the Cu wire is used to relieve the EM reliability concern. In recent years, traditional chemical vapor deposition (CVD) dielectric materials such as Si3N4 have been replaced by metal capping layers such as metal alloys of Cobalt-tungsten-phosphide (CoWP) due to increasing dielectric capacitance. Moving forward, a thinner, effective, and easy-to-process capping layer is a must for further reducing the dimensions of reliable interconnects. In this context, 3.35 Å atomically thin single-layer graphene (SLG) is a promising candidate to serve as both Cu diffusion barrier and capping layer, providing possibly the thinnest barrier. SLG potentially mitigates the increasing resistivity and decaying reliability at the same time, and thus is able to extend further Cu scaling. SLG barrier gives 3.3 times longer lifetime than 2 nm TaN, and comparable performance to 4 nm TaN, based on time dependent dielectric breakdown tests. Further reliability improvement of SLG is possible, by using single-crystal graphene to eliminate grain boundaries and a transfer-free growth to remove the transfer-induced defects. For multi-transferred SLG diffusion barriers, Cu diffuses vertically and laterally under the stress electric fields. A possible integration scheme with etched Cu processes and low-temperature in-situ graphene growth on patterned Cu wire is introduced. With this method, 1-2 layers of graphene improve EM lifetime of global Cu wires by 10× more than a 2 nm CoWP capping layer and achieve comparable lifetime to the industry-standard 3 nm CoWP. For local and intermediate Cu wires, low temperature grown graphene improves the electromigration lifetime by 2.4-3.5 times more than thermally annealed Cu wires. Besides, 30% lower resistivity and 5-30% higher breakdown current density are achieved with graphene-capped Cu. The breakdown mechanism with graphene/Cu composites is further studied through experiments and density functional theory (DFT) calculations. Pristine interfaces between graphene and Cu play a critical role in EM performance optimization. In summary, this dissertation presents advantages and challenges of employing graphene as the barrier and capping layer for ultimate scaled Cu wires. A direct integration scheme with traditional silicon CMOS and existing back-end-of-line (BEOL) processes are discussed. We first review challenges with scaling of BEOL technologies. To overcome these scaling problems, graphene as an interconnect material will be introduced in the second chapter. The third chapter discusses the advantages of graphene as a Cu diffusion barrier through benchmarking with the industrial standard material. Approaches to further improve graphene performance are identified, by studying graphene defects and thickness. In the fourth chapter, two different BEOL integration schemes of graphene with Cu interconnects are compared. One is compatible with the existing dual-damascene processes and another one is compatible with a new Cu etch processes. Chapter five examines advantages and challenges of applying low-temperature in-situ grown graphene as a Cu capping layer to improve the electro-migration reliability. Graphene capping layer performance is benchmarked to the industry-wide used material, CoWP. The breakdown mechanism for graphene/Cu composite structure and the scaling effect are studied. Lastly, a summary of contribution and conclusion will be provided in chapter six.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2018; ©2018 |
| Publication date | 2018; 2018 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Li, Ling |
|---|---|
| Degree supervisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Degree committee member | Pop, Eric |
| Degree committee member | Saraswat, Krishna |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Ling Li. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2018. |
| Location | https://purl.stanford.edu/cr113hf7159 |
Access conditions
- Copyright
- © 2018 by Ling Li
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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