From nanodevices to nanosystems : a case-study with carbon nanotubes and hetereogenous integration
Abstract/Contents
- Abstract
- The computing demands of future applications (such as abundant-data applications) far exceed the capabilities of today's electronics, and cannot be met by isolated improvements in transistor technologies or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency. However, emerging nanomaterials and nanodevices suffer from significant imperfections and variations, which made realizing working circuits, let alone transformative nanosystems, infeasible to date. As a case-study for realizing nanosystems, I present my work on carbon nanotube field-effect transistors (CNFETs), a leading candidate for energy-efficient and high-performance digital systems. Substantial imperfections and variations inherent to carbon nanotubes (CNTs), combined with low current densities, have restricted prior demonstrations to stand-alone transistors or logic gates, with severely limited performance, yield, and scalability. I describe how to overcome these major challenges through a combination of new CNFET process techniques and CNFET circuit design solutions. This imperfection-immune paradigm transforms CNTs from solely a scientifically-interesting nanomaterial into the foundation of working nanosystems, such as the first microprocessor and the first digital sub-systems built entirely using CNFETs. These are the first system-level demonstrations among promising emerging nanotechnologies for high-performance and highly energy-efficient digital systems. This approach (combined process techniques and circuit design solutions) also enables high-performance CNFETs with the highest current-drive to-date (which are, for the first time, competitive with similarly-scaled and similarly-biased silicon-based CMOS transistors from commercial foundries). All of the fabrication and design techniques are very-large-scale integration (VLSI)-compatible, and can be applied to arbitrary technology nodes; to illustrate, we experimentally demonstrate highly-scaled CNFETs corresponding to a 14 nm technology node. Beyond specific CNT technologies, I discuss work on building new architectures to achieve high degrees of energy efficiency for emerging data-intensive applications. Such new architectures are naturally enabled by a range of beyond-silicon emerging nanotechnologies (including CNTs). I demonstrate the first monolithically-integrated, three-dimensional (3D) nanosystem architectures with vertically-integrated layers of logic, memory, and sensing circuits. These include the largest nanosystem yet fabricated using beyond-silicon emerging nanotechnologies, with over 2 million CNFETs and over 1 million Resistive Random Access Memory (RRAM) cells, all integrated vertically over a conventional silicon substrate with over 1 million silicon transistors (all fabricated at the Stanford Nanofabrication Facility). With dense and fine-grained connectivity between sensing, storage and computation, such nanosystems can capture terabytes of data from the outside world every second, and produce "processed information" by performing in-situ classification of the sensor data using on-chip accelerators designed using CNFET logic. In summary, this thesis demonstrates a path for realizing a new generation of high-performance and energy-efficient nanoelectronic systems.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2016 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Shulaker, Max Marcel |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Howe, Roger Thomas |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Howe, Roger Thomas |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Max Marcel Shulaker. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2016. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2016 by Max Marcel Shulaker
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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