Design and optimization of processors for energy efficiency : a joint architecture-circuit approach

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The design of a digital system for energy efficiency often requires the analysis of trade-offs in both the circuit design and the architecture. To assist with this analysis, we present a novel optimization framework for performing joint design space exploration of architectural and circuit design spaces. In this approach, we use statistical inference/regression techniques to create a models of large micro-architectural design spaces from a small number of simulation samples. We then characterize the design trade-offs of each of the underlying circuits and integrate these with the higher level architectural models to define the joint circuit-architecture design space. By using posynomial forms for all our models, we are then able to formulate the optimization problem as a geometric program, enabling the use of convex optimization tools to efficiently search the joint design space. We apply this framework to study energy-performance trade-offs in general purpose microprocessor design. We consider six different high-level architectures, from a simple single-issue in-order processor to a quad-issue out-of-order processor. Optimizing across this space for different performance targets, we identify the order in which high-level architectural features should be considered as one seeks more performance; starting with a low-power single-issue in-order design, to increase performance efficiently one should first increase the issue-width to two, then add out-of-order execution, and finally increase the issue-width further to end with the quad-issue out-of-order processor if maximum performance is required. Extending our study to include the voltage scaling, we find that the results change dramatically. Our results show that architectural and circuit design techniques have a very rapidly changing marginal cost profile, with many options having either very low or very high marginal costs. Since the marginal cost of obtaining additional performance through voltage changes more slowly, we find that when we optimize the system jointly with voltage, the set of efficient architecture/circuit design features become confined to a small sweet spot for a large part of the design space. Thus, when optimized with voltage as a parameter, two high-level architectures--the dual-issue in-order processor and the dual-issue out-of-order processor--are efficient over almost the complete range of performance targets.


Type of resource text
Form electronic; electronic resource; remote
Extent 1 online resource.
Publication date 2010
Issuance monographic
Language English


Associated with Azizi, Omid Jalal
Associated with Stanford University, Department of Electrical Engineering
Primary advisor Horowitz, Mark (Mark Alan)
Primary advisor Kozyrakis, Christoforos, 1974-
Thesis advisor Horowitz, Mark (Mark Alan)
Thesis advisor Kozyrakis, Christoforos, 1974-
Thesis advisor Boyd, Stephen P
Advisor Boyd, Stephen P


Genre Theses

Bibliographic information

Statement of responsibility Omid Jalal Azizi.
Note Submitted to the Department of Electrical Engineering.
Thesis Ph.D. Stanford University 2010
Location electronic resource

Access conditions

© 2010 by Omid Jalal Azizi
This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).

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