Compiling image processing and machine learning applications to reconfigurable accelerators
Abstract/Contents
- Abstract
- Recent vision applications provide exciting new opportunities in photography, autonomous driving, and image generation. In turn, new hardware platforms have similarly risen to efficiently execute this class of applications. Effective compilers are necessary to seamlessly run these new applications on hardware accelerators. However, hardware accelerators use specialized memories to increase efficiency, which makes them challenging compilation targets. Addressing this issue requires changing the abstraction that the compiler uses to represent memories. In this dissertation, we present such a compiler. It compiles image processing and machine learning applications to dataflow accelerators. To create this system, we extend the Halide domain-specific language (DSL) to target streaming accelerators. Using new scheduling primitives, the user has full control over optimization decisions. These optimizations can be tailored to new hardware accelerators. We introduce a unified buffer abstraction to provide an interface between application definition and hardware memory configuration. This abstraction enables efficient hardware implementations while supporting the generality of applications that are represented in our abstraction. Our compiler enables compute sharing by generating designs that time-multiplex compute operations with low utilization. We demonstrate the effectiveness of this compiler by running applications on the Amber Coarse-Grained Reconfigurable Array (CGRA), designed by the Agile HArdware (AHA) group at Stanford.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2023; ©2023 |
| Publication date | 2023; 2023 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Setter, Jeff Ou |
|---|---|
| Degree supervisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Kjolstad, Fredrik |
| Thesis advisor | Kozyrakis, Christoforos, 1974- |
| Degree committee member | Kjolstad, Fredrik |
| Degree committee member | Kozyrakis, Christoforos, 1974- |
| Associated with | Stanford University, School of Engineering |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Jeff Setter. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2023. |
| Location | https://purl.stanford.edu/bn933dk7986 |
Access conditions
- Copyright
- © 2023 by Jeff Ou Setter
- License
- This work is licensed under a Creative Commons Attribution 3.0 Unported license (CC BY).
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