Doping and conformal non-planar growth of 2D semiconductors
Abstract/Contents
- Abstract
- To overcome the limitations of conventional transistor size scaling, recent proposals have been made to increase transistor density by vertically stacking transistors, in three dimensions (3D). However, conventional bulk semiconductors such as silicon are difficult to process in a vertical fashion due to their strong 3D bonding, and due to high-temperature growth required for high-quality films. To realize new scaling paradigms, new semiconductor materials are needed that can be easily processed for 3D heterogeneous integration, including on vertical sidewalls or trenches. While two-dimensional (2D) semiconductors offer promising properties for vertical scaling, 2D transistor performance has been insufficient and the deposition capabilities are not well understood. This thesis details my PhD work on improving 2D semiconductor transistor performance and demonstrating non-planar growth to realize the first vertical 2D transistor. First, I discuss analysis of experimental data on 2D transistors, highlighting key metrics and basic modeling. I then outline my efforts to standardize analysis and benchmarking of 2D transistors with the Python framework SemiPy and benchmarking website 2D Device Trends (http://2d.stanford.edu), introduced during this work. I also discuss the role of self-heating in 2D transistors and possible avenues to reduce their operating temperatures. Next, I present new doping techniques to increase the carrier concentration in n-type MoS2 and p-type WSe2 transistors, lowering their electrical contact resistance and increasing their on-state current. With modeling, I show that these doped 2D transistors are limited by thermal dissipation and could be comparable to state-of-the-art silicon transistors with improved heat sinking. Finally, I show that by utilizing van der Waals growth, 2D semiconductors can be conformally deposited on amorphous, non-planar features including sidewalls and high aspect ratio trenches. Such 2D semiconductor growth then enables vertical 2D transistors, which can have much smaller footprint than planar transistors, thereby offering higher transistor density. I then conclude with my own perspective on 2D semiconductor research and the necessary future work to enable commercial applications of 2D transistors
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2021; ©2021 |
| Publication date | 2021; 2021 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | McClellan, Connor |
|---|---|
| Degree supervisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Saraswat, Krishna |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Connor Jeffrey McClellan |
|---|---|
| Note | Submitted to the Department of Electrical Engineering |
| Thesis | Thesis Ph.D. Stanford University 2021 |
| Location | https://purl.stanford.edu/bd412rv0997 |
Access conditions
- Copyright
- © 2021 by Connor McClellan
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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