Design and fabrication of imperfection-immune carbon nanotube digital VLSI circuits
Abstract/Contents
- Abstract
- Carbon Nanotube Field Effect Transistors (CNFETs), consisting of semiconducting single walled Carbon Nanotubes (CNTs), show great promise as extensions to silicon CMOS. While there has been significant progress at a single-device level, a major gap exists between such results and their transformation into VLSI CNFET technologies. Major CNFET technology challenges include mis-positioned CNTs, metallic CNTs, and wafer-scale integration. This work presents design and processing techniques to overcome these challenges. Experimental results demonstrate the effectiveness of the presented techniques. Mis-positioned CNTs can result in incorrect logic functionality of CNFET circuits. A new layout design technique produces CNFET circuits implementing arbitrary logic functions that are immune to a large number of mis-positioned CNTs. This technique is significantly more efficient compared to traditional defect- and fault-tolerance. Furthermore, it is VLSI-compatible and does not require changes to existing VLSI design and manufacturing flows. A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 10^3-10^5, and overcomes the limitations of existing metallic-CNT removal techniques. The above techniques are demonstrated for complex logic structures using wafer-scale growth of (99.5%, estimated from Scanning Electron Micrographs) aligned CNTs on single-crystal quartz and wafer-scale CNT transfer from quartz to silicon. Such an integrated approach enables the first experimental demonstration of VLSI-compatible CNFET combinational circuits (e.g., computational elements such as half-adder sum-generators) and storage circuits (e.g., sequential elements such as D-latches) that are immune to inherent CNT imperfections. These experimentally-demonstrated circuits form essential building blocks for large-scale digital computing systems.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Patil, Nishant Parag | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering | |
| Primary advisor | Mitra, Subhasish | |
| Thesis advisor | Mitra, Subhasish | |
| Thesis advisor | Kozyrakis, Christoforos, 1974- | |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- | |
| Advisor | Kozyrakis, Christoforos, 1974- | |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Nishant Patil. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph. D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Nishant Parag Patil
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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