Cross-layer resilience to tolerate hardware errors in digital systems
Abstract/Contents
- Abstract
- Digital systems can be subject to errors in the underlying hardware (i.e., a signal produces incorrect logic value), which can prevent correct system operation. Ensuring resilient operation, i.e., the system operates correctly despite such hardware errors, is a major digital system design challenge. Sources of hardware errors include radiation-induced transient errors (soft errors), early-life failures caused by manufacturing defects, device degradation over time (circuit aging), and variability induced by manufacturing and operating conditions (e.g., supply voltage). With explosive growth in our dependency on digital systems, the ability to tolerate hardware errors is required for a large class of systems - from supercomputers to embedded systems. Moreover, with new generations of silicon CMOS technology, the susceptibility to hardware errors exacerbates. This dissertation focuses on errors caused by radiation and supply voltage variations. These error sources are particularly challenging since there is a short time window between when the conditions necessary to trigger an error occur and when the error is captured in a sequential element of the digital system. Existing resilience techniques for hardware errors are implemented at one or more layers of the system stack: circuit, logic, architecture, software, or algorithm layers. These are mostly one-off solutions that are generally expensive in terms of energy, power, execution time, or area (e.g., 25-100% or even higher energy costs). Several publications have therefore suggested the notion of cross-layer resilience, where multiple techniques from different layers of the system stack cooperate to achieve cost-effective error resilience, as a possible solution for designing low-cost resilient systems. Unfortunately, designers do not have a holistic understanding of how to create such cross-layer solutions. Several preconceptions regarding hardware error resilience therefore exist without detailed quantitative analysis. In this dissertation, I present an extensive study of cross-layer resilience. This first of its kind study starts with a comprehensive set of existing resilience techniques spanning circuit, logic, architecture, software, and algorithm layers. It then analyzes combinations of these techniques (i.e., cross-layer combinations) to derive cost-effective resilience approaches, quantify their cost-benefit tradeoffs, and provide insights into the causes for their (in)effectiveness. To enable this study, I have created a new software framework called CLEAR (Cross-Layer Exploration for Architecting Resilience). I demonstrate the broad applicability and effectiveness of CLEAR for a wide range of diverse hardware designs (general-purpose processor cores, uncore components such as cache controllers and memory controllers, and domain-specific hardware accelerators) over a rich set of cross-layer combinations of resilience techniques. For example, CLEAR thoroughly explores the soft error resilience design space consisting of a complete set of 586 cross-layer combinations and derives a resilience solution that achieves a 50x improvement in soft error rate (over an unprotected design) for out-of-order processor cores at only 2% energy cost (and no speed impact). CLEAR results have also been validated for industrial designs. The results of this study demonstrate that: 1. Circuit-level techniques are crucial for cost-effective error resilience solutions. 2. Application-level guidance (e.g., to identify vulnerable design blocks) is a key enabler for cost-effective resilience. However, since some application-level knowledge may be unavailable at design time, this study also presents an approach to reduce such dependencies for general-purpose processors. 3. Existing architecture- and software-level techniques for hardware error resilience are generally expensive (and their low-cost variants often provide too little resilience). In some cases, algorithm-level techniques can provide cost-effective resilience when properly combined with circuit-level techniques. 4. Some of the previously-published resilience techniques, in particular those implemented at the architecture and software layers, suffer from inaccurate evaluation. The CLEAR framework uses accurate evaluation methods to correct some of these incorrect conclusions and optimistic projections from the past. 5. Cost-effective protection from multiple error sources (radiation and supply voltage variations in this case) is achieved by combining resilience techniques that specifically target each error source.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2018 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Cheng, Eric | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. | |
| Primary advisor | Mitra, Subhasish | |
| Thesis advisor | Mitra, Subhasish | |
| Thesis advisor | Olukotun, Oyekunle Ayinde | |
| Thesis advisor | Tobagi, Fouad A, 1947- | |
| Advisor | Olukotun, Oyekunle Ayinde | |
| Advisor | Tobagi, Fouad A, 1947- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Eric Cheng. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2018. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2018 by Eric C Cheng
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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