Network interface design for low latency datacenter applications
Abstract/Contents
- Abstract
- Ethernet network interfaces in commodity systems are designed with a focus on achieving high bandwidth at low CPU overheads, while often sacrificing latency. This approach is appropriate when software request processing is measured in milliseconds and the interface latency is not an issue. However, recent low latency software efforts in datacenters, such as memcached and RAMCloud, have lowered the software times into the microsecond range. Therefore, the network interface has been promoted into a significant contributor to the overall latency. This thesis presents NIQ: a low latency network interface design optimized for request-response based datacenter applications. NIQ features separate small and large packet interfaces that efficiently send and receive packets with a minimum number of PCIe transitions. A NIQ prototype is built on an FPGA development platform to facilitate the design space exploration and evaluation. The results demonstrate that the proposed interface is capable of 4.7 us application round trip latencies without meaningful negative impact on CPU power or throughput. The NIQ interface supports one independent transmit and receive queue per CPU core, thus enabling datacenter applications reaching higher throughput through parallelization. This thesis argues that multi-threaded multi-queue designs are prone to high latency variance which manifests itself as high tail latency. To combat the high tail latency and further improve the average latency, this thesis presents NeRD: a mechanism for dispatching arriving network requests to the appropriate processor core. NeRD is an application inspired hardware module that combined with NIQ network interface achieves low average and low tail latencies. The NIQ+NeRD combination achieves tail latency improvements by efficiently load balancing requests across processor cores. FPGA prototype results show that under the request load of 80% of maximum, the 95th percentile latency stays within a factor of two of the median latency. Additionally, NeRD provides hardware support for quickly scaling between one and multiple cores, depending on the current request load. The NIQ and NeRD prototype's latency results were found to be heavily dependent on the CPU's power management settings. To quantify the effects of modern power management, an investigation of latency-power tradeoffs was conducted. In particular, this thesis explores the tradeoffs between using interrupts and polling as notification mechanisms.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Flajslik, Mario | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. | |
| Primary advisor | Rosenblum, Mendel | |
| Thesis advisor | Rosenblum, Mendel | |
| Thesis advisor | Kozyrakis, Christoforos, 1974- | |
| Thesis advisor | Ousterhout, John K | |
| Advisor | Kozyrakis, Christoforos, 1974- | |
| Advisor | Ousterhout, John K |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Mario Flajslik. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Mario Flajslik
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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