DSLs to reconfigurable hardware : design of the spatial language and compiler
Abstract/Contents
- Abstract
- In recent years, the computing landscape has seen an increasing shift towards specialized accelerators. Reconfigurable architectures like field programmable gate arrays (FPGAs) are particularly promising for accelerator implementation as they can offer performance and energy efficiency improvements over CPUs and GPUs while offering more flexibility than fixed-function ASICs. Unfortunately, adoption of reconfigurable hardware has been limited by their associated tools and programming models. The conventional languages for programming FPGAs, hardware description languages (HDLs), lack abstractions for productivity and are difficult to target directly from higher level languages. Commercial high level synthesis (HLS) tools offer a more productive programming solution, but their mix of software and hardware abstractions is ad-hoc, making both manual and automated performance optimizations difficult. As demand for customized accelerators has grown, so too has the demand by software engineers and domain experts for domain-specific languages (DSLs) which provide higher levels of abstraction and hence improved programmer productivity. Unfortunately, in the domains of machine learning and data analytics, most domain-specific methods for generating accelerators are focused on library-based approaches which generate hardware on a per-kernel basis, resulting in excessive memory transfers and missing critical cross-kernel optimizations. As DSLs become more ubiquitous, this approach will not scale. This dissertation describes a new system for compiling high-level applications in domain specific languages to hardware accelerator designs that addresses these productivity, generality, and optimization challenges. To improve results above kernel-based approaches when programming in domain-specific languages, we introduce a waypoint between DSLs and HDLs: a new intermediate abstraction dedicated to representing parameterized accelerator designs targeting reconfigurable architectures. Starting from a common intermediate representation for high-level DSLs based on parallel patterns, we first describe the cross-kernel optimizations the system performs and the methods which used to lower the entire application graph into a parameterized design in the intermediate hardware abstraction. We then describe our implementation of this intermediate abstraction, a language and compiler called Spatial. We discuss some of the compiler optimizations Spatial enables, including rapid design parameter tuning, pipeline scheduling, and memory banking and partitioning. The end result is a compiler stack which can take as input a high-level program in a domain-specific language and translate it into an optimized, synthesizable hardware design coupled with runtime administration code for the host CPU.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2019; ©2019 |
| Publication date | 2019; 2019 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Koeplinger, David Alan | |
|---|---|---|
| Degree supervisor | Olukotun, Oyekunle Ayinde | |
| Thesis advisor | Olukotun, Oyekunle Ayinde | |
| Thesis advisor | Horowitz, Mark (Mark Alan) | |
| Thesis advisor | Zaharia, Matei | |
| Degree committee member | Horowitz, Mark (Mark Alan) | |
| Degree committee member | Zaharia, Matei | |
| Associated with | Stanford University, Department of Electrical Engineering. |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | David Alan Koeplinger. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2019. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2019 by David Alan Koeplinger
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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