Analysis and design of high density RRAM arrays
Abstract/Contents
- Abstract
- Among the emerging nonvolatile memory technologies that could potentially replace flash memory, RRAM (resistance change random access memory) is particularly appealing thanks to its small size, short switching time, low operation voltage, and good compatibility with the standard CMOS process. However, for RRAM to be a cost-competitive candidate for high-density and high-capacity commercial products, some architectural-level challenges must be tackled. In this dissertation, research results that advance the design of high-density RRAM arrays are presented. After a brief review of the RRAM device and array fundamentals, a complete analysis of cross-point arrays in read operations is presented. The analysis concludes with a proposal for a new bias scheme that increases the read margin of the cross-point RRAM array. A compact, one-transistor-four-RRAM (1T4R) array architecture, with corresponding read/write and decoding schemes, that achieves high RRAM density is then introduced. Circuit simulation results that validate this new architecture and a proof-of-concept test chip with fully integrated RRAM devices are described. For this test chip, a particular sequence to form the cross-point RRAM array is presented. Measurement results of successful array operations demonstrate the feasibility of high-capacity integration of the proposed architecture. The research then focuses on the scaling effects of on-chip interconnects on RRAM array performance. Due to the continuously shrinking process feature size, the voltage drop along the interconnect gradually reduces the voltage available to operate the RRAM device. To more efficiently analyze this effect for an arbitrary array size, a compact array model is developed. Simulations using this model are shown to quantitatively illustrate the maximum achievable array size in the future. Interconnect electromigration and parasitic capacitance effects are then considered at the end.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Yeh, Chih-Wei Stanley | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. | |
| Primary advisor | Wong, S. Simon | |
| Thesis advisor | Wong, S. Simon | |
| Thesis advisor | Lee, Thomas H, 1959- | |
| Thesis advisor | Nishi, Yoshio, 1940- | |
| Advisor | Lee, Thomas H, 1959- | |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Chih-Wei Stanley Yeh. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Chih-Wei Yeh
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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