Device technology for nanoscale III-V compound semiconductor field effect transistors
Abstract/Contents
- Abstract
- As silicon CMOS technology reaches its fundamental scaling limits, alternative materials such as high mobility III-V compounds have proven to be strong contenders for extending high performance logic. However, most promising demonstrations of III-V FET/HEMTs have micron-scale source/drain spacing despite gate lengths on the nanometer scale. III-V semiconductor devices have historically relied on alloyed ohmic contacts which require large spacings to prevent shorting between the source and drain after alloying, where contacts can diffuse up to hundreds of nanometers. This severely limits the scalability of III-V logic technology. Non-alloyed contacts offer a practical route to greatly reduce the III-V device footprint for application in future technology nodes. In this dissertation, I demonstrate a route to non-alloyed contacts by shifting the pinned III-V Fermi level to reduce the metal/n-GaAs and metal/n-InGaAs Schottky barrier heights. The Fermi level is controlled by the insertion of thin dielectrics in a metal-insulator-semiconductor (MIS) contact structure. The MIS contact is studied across a wide range of metal and dielectric materials, and found to have great flexibility in the material selection. I will also discuss the use of bi-layer high-[kappa] dielectrics, and report results which show that despite an overall thicker dielectric, there is an additional reduction in the barrier height and contact resistance beyond that of a single dielectric MIS. This MIS contact is then integrated in an InGaAs MOSFET as a non-alloyed source/drain contact, though it can also be applied to Schottky Barrier FETs. I will conclude by discussing possible physical mechanisms of the observed barrier height reductions, by examining the effects of fixed charge and electronic dipoles.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2011 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Hu, Jenny Ruey-Chen | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering | |
| Primary advisor | Saraswat, Krishna | |
| Primary advisor | Wong, Hon-Sum Philip, 1959- | |
| Thesis advisor | Saraswat, Krishna | |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- | |
| Thesis advisor | Nishi, Yoshio, 1940- | |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Jenny Ruey-Chen Hu. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph. D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Jenny Ruey-Chen Hu
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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