Modeling of III-V nanoscale field-effect transistors for logic circuits
Abstract/Contents
- Abstract
- As silicon CMOS technology continues to scale down its minimum critical dimension, it becomes increasingly difficult to enhance device switching speed due to fundamental limitations. Innovations in device structure and materials are pursued to accommodate improvement in performance as well as reduction in transistor size. For beyond-22-nm CMOS technology, III-V channel FETs are considered as a compelling candidate for extending the device scaling limit of low-power and high-speed operation, owing to their superb carrier transport properties and recent experimental advancements. In this thesis, device simulation, compact modeling, circuit design, circuit performance assessment and estimation of III-V logic transistors are carried out to study key considerations such as device pitch, parasitics, and the importance of PMOS for circuit-level performance. To effectively connect device characteristics with circuit design, a physics-based compact model for digital logic is constructed. The model encompasses effects such as field-confined and spatially-confined trapezoidal quantum well sub-band energies, gate leakage tunneling current and parasitic capacitance. The developed compact model contains only three fitting parameters and is verified by experiment and circuit simulations. The compact model enables other bodies of work for the purpose of circuit-level design and performance estimation. To demonstrate the capability of the model in a circuit environment we apply the compact model to composite circuits such as FO4 inverter chains and SRAM cache to evaluate and project performance and power trends for beyond-22-nm technology.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Oh, Saeroonter | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering | |
| Primary advisor | Saraswat, Krishna | |
| Primary advisor | Wong, Hon-Sum Philip, 1959- | |
| Thesis advisor | Saraswat, Krishna | |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- | |
| Thesis advisor | Nishi, Yoshio, 1940- | |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Saeroonter Oh. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Saeroonter Oh
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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