Towards sub-10 nm phase change memory - device structure and array analysis
Abstract/Contents
- Abstract
- With the ubiquitous presence of today's portable devices, non-volatile memories (NVMs), which can store information when power is turned off, have witnessed unprecedented progress in the last few decades. The sustained growth in NVM technologies is fueled by the continued shrinking of device sizes to ever smaller dimensions. In 2012, Flash, the current mainstream of NVM technology, has already been scaled down to 19nm in manufactured products. Looking forward, flash technology is facing fundamental physical limitations such as charge leakage issue beyond 15nm. To enable continued scaling, many alternative memory concepts and new materials, which have unique characteristics not available in Flash, have been exploited and are leading transformations in the design of the memory hierarchy. Among them, phase change memory (PCM) offers high scalability, low fabrication cost, fast programming speed, good endurance and multi-level cell capability (MLC), and is widely considered as one of the most promising candidates for the next-generation NVMs. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. Moreover, for memory array implementation, additional challenges coming from the sneak path leakage and wire scaling severely limit the maximum array size one can achieve. A careful co-design between memory device structure and array configuration beyond sub-10nm regime is hence imperative. In this thesis, novel structures of PCM cells working close to its ultimate scaling limit is proposed and demonstrated. Comprehensive analyses and discussions on the various challenges of the design of cross-point memory arrays towards sub-10nm feature sizes are presented. To explore the scaling limit of PCM cells, carbon nanotube (CNT), which is a naturally single-digit-nm material, is utilized as the memory electrode. A fully functional cross-point PCM cell utilizing CNTs as the bottom memory electrode is proposed and constructed. The use of CNT bottom electrode (BE) brings the lithography-independent critical dimension down to 1.2 nm and effectively confines the conducting GST path to sub-5nm2. The ultra scaled device area contributes to a large programming current reduction to 1.4 [mu]A, which is two orders of magnitude smaller than the state-of-the-art, and a record-low programming energy to 210 fJ. Our cross-point PCM cell exhibits stable switching characteristics, good read immunity and decent resistance distribution. Measured electrical characteristics validate the advantage of device scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultra-dense PCM array down to 1.8nm node technology. For practical storage memory system, large numbers of single memory cells are integrated together to construct a memory array. The resistive cross-point memory architecture offers the highest device density, yet, it suffers from substantial sneak path leakages which result in a large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnect wires further degrades the output signal, and imposes an additional limitation on the maximum allowable array size. To analyze the challenges associated with the design of resistive cross-point memory array, a new methodology for the worst case analysis and a reduced circuit model for cross-point memory arrays are introduced. Using this model, the size limiting factors of cross-point memory arrays without selection devices are analyzed considering both the array data pattern dependence and memory cell parameter dependence. Next, the impact of bit line and word line wire scaling on the write/read margin, energy dissipation, speed and reliability of resistive cross-point memory array are quantitatively examined for wire sizes down to the sub-10nm node. The impending resistivity increase due to wire dimensional scaling results in significantly degraded write and read windows, substantial interconnect energy, increased wire latency and exacerbating reliability. They thereby preclude the realization of large-scale cross-point memory array with minimum feature sizes beyond the 10 nm node. A rethink in the design methodology of cross-point memory to incorporate and mitigate the scaling effects of word line/bit line is hence necessary. As an example of a potential solution to these challenges, a new concept of using local back gate (LBG) carbon nanotube field-effect transistor (CNFET) as memory electrode, interconnect, and selection device for cross-point memory arrays is proposed. The improvement of the cross-point array performance promises the possibility of an integrated memory-carbon structure for sizes beyond 10nm technology node.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Liang, Jiale | |
|---|---|---|
| Associated with | Stanford University, Department of Electrical Engineering | |
| Primary advisor | Wong, Hon-Sum Philip, 1959- | |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- | |
| Thesis advisor | Nishi, Yoshio, 1940- | |
| Thesis advisor | Wong, S. Simon | |
| Advisor | Nishi, Yoshio, 1940- | |
| Advisor | Wong, S. Simon |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Jiale Liang. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Jiale Liang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
Also listed in
Loading usage metrics...